The present invention relates generally to semiconductor devices and more particularly to improved apparatus and methods for coupling local IO lines with sense amplifiers for accessing ferroelectric and other type memory cells in memory devices.
Ferroelectric memory devices, like other semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) cell configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically include one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage.
The ferroelectric memory cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of platelines and wordlines by address decoding circuitry. Such devices are typically organized internally into blocks, sections, segments, rows and columns. For example, a 64M device may include 8 blocks of 8M each, the blocks each consisting of 8 sections which contain 32 segments, Each segment contains 512 words or rows of 64 bits or columns per word. When a data word is read, the cell data from the corresponding bit in each of the 64 columns is sensed using 64 individual sense amplifiers associated with the individual data cell columns.
Data in a ferroelectric data cell is read by connecting the cell capacitor on a first bitline and a reference voltage on a complementary bitline to the input terminals of a differential sense amp. The plateline of the accessed cell is then pulsed. This provides a differential voltage on the bitline pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between a voltage (Vxe2x80x9c0xe2x80x9d) associated with a capacitor charged to a binary xe2x80x9c0xe2x80x9d and that of the capacitor charged to a binary xe2x80x9c1xe2x80x9d (Vxe2x80x9c1xe2x80x9d). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is amplified and applied to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local IO lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device.
In a typical ferroelectric memory read sequence, two sense amp terminals or bitlines are initially equalized to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp terminals via the bitline to which the cell is connected. Thereafter, a reference voltage is connected to the remaining sense amp terminal, and the sense amp senses the differential voltage across the terminals and latches a voltage indicative of whether the target cell was programmed to a binary xe2x80x9c0xe2x80x9d or to a xe2x80x9c1xe2x80x9d. The sense amp terminals are then coupled to local IO lines, which were previously precharged to a predetermined voltage state, such as VDD. The sense amp drives one of the local IO lines to a different voltage state, by which the read data state is passed to an IO buffer circuit. In a write operation, the sense amp and bitline terminals are connected to the local IO lines, which are driven to opposite voltage states depending on the data to be written. One bitline connects to the ferroelectric memory cell for storage of the data written into the ferroelectric capacitor.
FIGS. 1 and 2 illustrate a ferroelectric memory device 2 organized in a folded bitline architecture, wherein a segment portion of the device 2 has 512 rows (words) and 64 columns (bits) of data storage cells CROW-COLUMN, where each column of cells is accessed via a pair of complimentary data bitlines BLCOLUMN and BLCOLUMNxe2x80x2. One column of the device 2 is illustrated in FIG. 2, in which cells C1-1 through C1-64 form a data word accessible via a wordline WL1 and complimentary bitline pairs BL1/BL1xe2x80x2 through BL64/BL64xe2x80x2. The cell data is sensed during data read operations using sense amp circuits 12 (S/A C1 through S/A C64) associated with columns 1 through 64, respectively. In a typical folded bitline architecture ferroelectric memory device, the cells CROW-COLUMN individually include one or more ferroelectric cell capacitors and one or more access transistors to connect the cell capacitors between one of the complimentary bitlines associated with the cell column and a plateline, where the other bitline is selectively connected to a reference voltage.
In the device 2, the sense amps 12 associated with even numbered columns are located at the bottom of the segment, whereas sense amps 12 associated with odd numbered columns are located at the top of the segment. Shared reference generators 8xe2x80x2 and 8 are provided at the top and bottom of the segment columns, respectively. An even column reference generator 8 is provided at the bottom of the segment columns for providing a reference voltage for even numbered columns and an odd column reference generator 8xe2x80x2 is provided at the top of the columns for the odd numbered columns. The reference voltages from the generators 8, 8xe2x80x2 are coupled to one of the bitlines in the columns using one of a pair of switches 8a, 8b, depending upon whether an even or odd numbered wordline is selected. In reading the first data word of the illustrated segment along the wordline WL1 in the device 2, the cells C1-1 through C1-64 are connected to the sense bitlines BL1, BL2 . . . , BL63, and BL64 while the complimentary reference bitlines BL1xe2x80x2, BL2xe2x80x2 . . . , BL63xe2x80x2, and BL64xe2x80x2 are floating. The reference bitlines BL1xe2x80x2, BL2xe2x80x2 . . . BL63xe2x80x2, and BL64xe2x80x2 are thereafter connected to the reference voltage generators 8, 8xe2x80x2.
As illustrated in FIG. 2, the ferroelectric memory cells 4 include capacitors CFE constructed with ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor CFE in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
In ferroelectric memories, as well as conventional DRAMs, the connection of local IO lines LIO/LIOxe2x80x2 to the sense amp terminals SABL/SABLxe2x80x2 is timed during read operations to occur a certain time after the connection of the sense amp terminals SABL/SABLxe2x80x2 to the memory cell 4 and the reference 8. This is done to prevent disturbance in the sensing operation of the sense amp 12, where the data bitlines BL1/BL1xe2x80x2 are initially separated by only a small voltage difference (e.g., tens or hundreds of millivolts). In this regard, the local IO lines, which are precharged at the beginning of the read operation, are typically fairly large in capacitance. As a result, charge from the local IO lines is provided to the sense amp terminals upon connection therewith, which may disturb the amplification operation in the sense amp if connected before sufficient amplification has occurred, leading to degradation of sense margin, and possibly to incorrect data being provided to the local IO buffering circuitry (data polarity flipping). Thus, the timing of LIOS is controlled so as to actuate the access transistors 20a and 20b a sufficient time after the sense amp is enabled by turning on transistors MP2 and MN2 via sense amp enable signals SE and SExe2x80x2.
In DRAMs, the same LIOS timing may be employed for both read and write cycles, wherein LIOS is actuated to connect the sense amp 16 with the local IO lines LIO and LIOxe2x80x2 a certain time after the sense amp 12 is enabled. However, ferroelectric memory cells typically store a larger charge density and have larger capacitance values than do conventional DRAM cells. Because of the larger capacitance and higher charge density, more time is required to write a ferroelectric memory cell 4 than a typical DRAM data cell. Thus, in the ferroelectric memory device 2, it may be desirable to provide the LIOS signal relatively early in a write cycle to allow the sense amp to fully program the ferroelectric memory cell capacitor. However, as discussed above, minimum timing requirements are set during read operations to prevent connection of local IO lines LIO/LIOxe2x80x2 from interfering with sense amp amplification of data read from the cell. Thus, it is not always possible to simply provide the LIOS signal earlier in both the read and write operations for ferroelectric memory devices.
One solution might be to provide the local IO select signal LIOS earlier in a write cycle than in a read cycle. However, memory applications require selective write masking wherein one or more bits in a data word may be written while others are not. In such a masked-write operation, the cells associated with the masked bits undergo a pseudo read operation, in which the existing cell data is read out to the sense amp, and then restored back into the cell. In the case of a masked write, early assertion of the LIOS signal could lead to the above described failure mechanism for the masked bit cells. Thus, there is a need for improved methods and apparatus for coupling ferroelectric memory sense amps with local IO lines to facilitate memory cell access in both read and write operations.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention provides memory devices, such as ferroelectric memories and sensing systems therefor, in which one or more local IO lines are selectively coupled with a sense amp earlier in a write operation than in a read operation. This may be employed to facilitate proper charging of memory cell capacitors during writing, while allowing mitigation of the above-mentioned sensing disturbance during reading. In certain implementations, moreover, the invention allows foregoing the early write operation coupling where a masked write operation is taking place. Thus, the invention finds utility in ferroelectric memory devices which allow a user to selectively write one or more bits along a wordline while masking others, wherein the written bit cells undergo a write operation with the early sense amp/local IO line coupling, and the masked bit cells undergo a pseudo read operation using the later coupling. The invention may be employed in association with any type of sense amp and memory cell circuitry and architectures.
In one example, first and second IO selection circuits or selection systems are provided for selectively coupling a sense amp with one or more associated local IO lines. A first IO select circuit is coupled with a local IO line and the sense amp, which selectively couples them to provide data from the sense amp to the local IO line during a read operation. A second IO select circuit is also coupled with the local IO line and the sense amp, which operates to selectively couple the local IO line with the sense amp during a write operation.
In one implementation, illustrated and described below, the second IO select circuit comprises first and second switching devices connected in series between the local IO line and the sense amp, which operate to selectively couple the sense amp and the local IO line with one another according to a write control signal and a voltage on a complimentary local IO line during the write operation. The inventors have appreciated that the invention may be employed to provide enough time for proper programming of ferroelectric memory cell capacitors during normal write operations while refraining from such coupling during masked-write and read operations until the sense amp has sufficiently amplified cell data voltages to avoid or mitigate sense amp disturbance problems associated with connection of the local IO lines thereto.
In this example, where the associated IO buffer refrains from providing data to the local IO lines, such as where a write mask is being used, the second IO select circuit selectively refrains from early coupling of the sense amp and the local IO line. In this case, the first IO select circuit provides for later coupling according to the timing constraints appropriate for a normal read cycle, whereby the pseudo read operation is not disturbed by premature connection of the local IO lines. In another example, the first IO select circuit couples the local IO line with the sense amp a second time period after the sense amp is enabled during the read operation, and the second IO select circuit couples the local IO line with the sense amp a first time period before the sense amp is enabled during a write operation, in which the first time period may be zero.
Another aspect of the invention provides methods for selectively coupling a sense amp to a local IO line during a memory access operation in a memory device. The methods comprise enabling the sense amp, coupling the sense amp with the local IO line a first time period prior to or coincident with enabling the sense amp during a write operation, and selectively coupling the sense amp with the local IO line a second time period after enabling the sense amp during a read operation.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.